The present invention relates to a packet switch for high-speed packet communications.
In parallel with the rapid progress in the optical fiber transmission and high-speed VLSI (Very Large Scale Integrated Circuit) technologies, there is an increasing demand for new communication services of the kind using extremely fine pictures, for example. While broadband ISDN's (Integrated Services Digital Networks) are available as means for handling a plurality of different kinds of information such as voice and pictures collectively, how to multiplex and switch such various kinds of information is a critical consideration. A STM (Synchronous Transfer Mode) switching scheme and a ATM (Asynchronous Transfer Mode) switching scheme have been proposed to implement the multiplexing and switching system of broadband ISDN's.
With an ATM switching scheme, motion picture, voice or similar continuous data and a still picture or similar burst data are packetized into fixed length packets and the packets are exchanged. The ATM switching scheme does not require that the terminal equipment and transmission channels be synchronous and be provided with the same data rate. This kind of switching scheme is therefore advantageous over an STM switching scheme with regard to the ease of system expansion and development. An example of packet switches applicable to an ATM switching scheme has been taught by Thomas et al in a paper entitled "ASYNCHRONOUS TIME-DIVISION TECHNIQUES: AN EXPERIMENTAL PACKET NETWORK INTEGRATING VIDEO COMMUNICATION", International Switching Symposium, (ISS) '84 Florence, May 7-11, 1984, Session 32 C, Paper 2 (Reference 1). As described later in detail, the packet switch disclosed in this paper has a single buffer memory which is shared by multiple input lines and multiple output lines, and it switches packets by controlling the write and read addresses of the buffer memory. The address control of the buffer memory is effected by using address queues which are assigned to individual output lines, a waiting address queue which shows addresses of stored packets, an idle address queue which shows idle areas of the memory, etc. While this system can be implemented with a relatively small buffer memory capacity because multiple output lines share the memory, it requires complicated control for the shared use of the memory. Specifically, idle address queue and waiting address queues associated with the individual output lines are required, and addresses have to be interchanged between the idle address queue and the waiting address queues every time a packet is written in or read out of the buffer memory. Moreover, when a certain address in a queue is lost or doubled by noise or some malfunction, there occurs in the buffer memory an unused area or, in the worst case, false data is overwritten on a packet to delete the latter or a packet is fed out to an unexpected output line. Such occurrences cannot be eliminated without resorting to extra means for detecting unusual conditions and, because such detection is difficult, the processing is complicated.